FPGA Design Intern

Key Responsibilities

• 0–1 years of hands-on experience in implementing designs on FPGA
• Strong expertise in RTL coding using VHDL/Verilog/System Verilog
• Understanding of FPGA design flow including constraint definition, synthesis, floor planning, place & route, and timing closure
• Create block-level design documentation
• Write testbenches and sequences in SystemVerilog
• Work with lab equipment for validation and testing
• Familiarity with standard interface protocols (e.g., SPI, I2C, UART, etc.)
• Knowledge of modern FPGA architectures
• Exposure to scripting languages for automation

Preferred Experience

• Hands-on experience with FPGA design tools like Libero
• Experience with Tcl/Perl/Python scripting
• Good debugging skills (both hardware and software)
• Understanding of Clock Domain Crossing (CDC) checks
• Knowledge of synthesis and static timing analysis
• Familiarity with FPGA hardware design is an added advantage

Benefits

• Real-world exposure to cutting-edge space technology projects
• Mentorship from experienced FPGA and space systems engineers
• Collaborative, growth-oriented team environment
• Fun, engaging, and fast-paced work culture