Formal Verification Lead (DDR PHY)

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SMTS SILICON DESIGN ENGINEER

THE ROLE:

AMD is looking for a role of Senior Member of Technical Staff, a leader passionate about driving the cutting-edge formal verification techniques for AMD's DDR PHY IP design. The ideal candidate will have proven experience in driving cutting-edge formal verification methodology to achieve industry leading verification quality and productivity under tight schedule. In this role the candidate will work with architecture team and design team and global formal verification team to define our formal verification roadmap, strategy, methodology, infrastructure and expand formal verification adoption through project execution. The candidate will be the primary point of contact for all DDR PHY formal verification practice.

You will be a member of a Circuits and Technology group working on latest and upcoming DDR PHY designs.

THE PERSON:

The ideal candidate should have demonstrated rich experience in formal verification techniques and must possess leadership skills to influence and drive the whole formal verification team. Able to communicate effectively and work optimally with different teams across the organization. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

• Define long-term strategy for formal verification expansion and steer the technical roadmap.
• Develop cutting-edge formal verification methodology to cover the DDRPHY designs, includes both datapath and control logic. Scale formal verification to big and critical design for bug-free quality. Expand formal verification adoption to the whole IP development life cycle. Resolve challenging convergence issue through world class formal verification techniques like induction, reduction, abstraction, etc.
• Define and drive the best-in-class formal verification infrastructure to improve formal verification productivity. Enable verification engineers to adopt this advanced verification technology without deep formal verification knowledge
• Lead the research group for emerging formal verification domains like security, safety, low power, architect level formal verification, etc. Explore the feasibility of formalizing ISA and memory model for GFXIP design
• Stay informed of latest trends and innovations in formal verification. Develop technical relationship with broader AMD Design community and peers. Drive cross-department innovation and collaboration inside AMD

PREFERRED EXPERIENCE:

• In-depth knowledge in formal verification algorithms, engines and use cases
• Proven expertise in system Verilog assertion and abstract model development
• Expert user of formal verification tool from both academy and EDA vendors (JasperGold, VC formal, Murphi, theorem prover)
• Proven track record of delivering high quality verification under tight schedule.
• Proven expertise in developing formal verification infrastructure for FPV, DPV and other use cases is strongly preferred
• Knowledge of DDR PHY and DFI interface is preferred.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

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Benefits offered are described: .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's Responsible AI Policy is available

This posting is for an existing vacancy.