Formal verification engineer

Formal Verification Engineer

Location: Bengaluru / Hyderabad

Work Mode: On-site / Hybrid

Experience: 4+ years of relevant experience in Formal Verification

Role Overview

We are hiring a Formal Verification Engineer with strong hands-on experience in formal verification methodologies for complex ASIC/SoC designs. The role involves developing and executing formal verification strategies, property development, debugging, and verification closure. Candidates should have practical experience with Cadence JasperGold and/or Synopsys VC Formal, along with strong SystemVerilog Assertions (SVA) knowledge.

Key Responsibilities

• Develop and execute formal verification plans for complex ASIC/SoC designs.
• Perform Formal Property Verification (FPV) at block and subsystem levels.
• Develop properties, assertions, assumptions, and cover statements using SystemVerilog Assertions (SVA) or PSL.
• Perform Sequential Equivalence Checking (SEC) across RTL and design transformations.
• Execute Security Path Verification (SPV) for security-sensitive data and control paths.
• Perform connectivity verification using formal methodologies.
• Verify low-power design intent and low-power functionality using formal techniques.
• Analyze formal verification failures, counterexamples, unreachable states, and convergence issues.
• Debug RTL and formal properties in collaboration with RTL design and verification teams.
• Improve proof convergence through abstraction, constraints, decomposition, and formal methodology techniques.
• Develop and maintain automation scripts using Python, Perl and/or Tcl.
• Track formal verification coverage, proof status, waivers, and verification closure.

Required Qualifications

• B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Computer Science, VLSI, or a related discipline.
• 4+ years of relevant hands-on experience in Formal Verification.
• Strong understanding of ASIC/SoC design and verification methodologies.
• Hands-on experience with at least one industry-standard formal verification tool.
• Strong knowledge of property specification and assertion-based verification.
• Proficiency in RTL languages such as SystemVerilog, Verilog, or VHDL.
• Strong debugging and problem-solving capabilities.

Technical Skills Formal Verification

• Formal Property Verification (FPV)
• Sequential Equivalence Checking (SEC)
• Security Path Verification (SPV)
• Connectivity Verification
• Low-Power Formal Verification
• Assertion-Based Verification
• Formal Coverage and Verification Closure
• Proof Convergence and Debug

Formal Verification Tools

• Cadence JasperGold / Jasper
• Synopsys VC Formal

Property Specification & RTL

• SystemVerilog Assertions (SVA)
• Property Specification Language (PSL)
• SystemVerilog
• Verilog
• VHDL

Scripting & Automation

• Python
• Perl
• Tcl

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