Formal Verification Engineer

Project Role : Formal Verification Engineer

Project Role Description : Ensure design correctness using mathematical methods like model checking and equivalence checking, without relying on simulation. Detect corner-case bugs early in the design cycle to improve quality and reduce verification time.

Must have skills : SoC Verification

Good to have skills : NA

Minimum 12 Year(s) Of Experience Is Required

Educational Qualification : 15 years full time education

Summary:

As a Formal Verification Engineer, you will ensure design correctness using mathematical methods such as model checking and equivalence checking. Your typical day will involve analyzing design specifications, developing formal models, and applying verification techniques to detect corner-case bugs early in the design cycle, ultimately improving quality and reducing verification time.

Roles & Responsibilities:

Experience in full chip verification cycle: test planning, verification code writing, running tests, RTL debug, and verification closure.

Create and use verification components and environments in standard verification methodologies.

Collaborate with design engineers to debug tests and deliver functionally correct design blocks.

Professional & Technical Skills:

Strong expertise in chip verification with 7–10 years or 10+ years of experience.

Proficiency in SystemVerilog/UVM or Specman/E.

Preferred: Experience in full-chip verification of large SoC chips.

Additional Information:

Ability to work on complex SoC designs and ensure functional correctness.

Strong problem-solving and debugging skills., 15 years full time education