Formal Verification

Description

We are seeking a skilled Formal Verification Engineer to join our team in India. The ideal candidate will have substantial experience in formal verification of hardware and software systems, with a focus on ensuring the correctness of designs through rigorous analysis and verification methodologies.

Responsibilities

• Develop formal verification models for hardware and software systems.
• Perform formal verification of designs to ensure correctness and compliance with specifications.
• Collaborate with design and verification teams to identify verification requirements.
• Analyze verification results and prepare detailed reports on findings.
• Enhance and maintain formal verification tools and methodologies.
• Participate in design reviews and provide feedback on design correctness.
• Stay updated with the latest trends and advancements in formal verification techniques.

Skills and Qualifications

• Master's or Bachelor's degree in Computer Science, Electrical Engineering, or a related field.
• Strong knowledge of formal verification techniques and tools such as Model Checking, Theorem Proving, etc.
• Proficiency in programming languages such as C/C++, SystemVerilog, or similar.
• Experience with formal verification tools like Cadence JasperGold, Synopsys VC Formal, or similar is a plus.
• Strong analytical and problem-solving skills.
• Ability to work collaboratively in a team environment.
• Excellent communication skills, both verbal and written.