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ALTEN Calsoft Labs

Field-Programmable Gate Arrays Engineer

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Job Description

RTL FPGA Design Engineers

Experience : 1-3 years

Location : Hyderabad

Expertise RTL Coding in Verilog, System Verilog or VHDL · Strong understanding of FPGA flow, Logic design, Digital design etc. · Knowledge in Xilinx FPGA architecture · Good Knowledge in Tcl, Python scripting.

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Job ID: 144750953

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