Engineer II – DFT

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Job Description:

• We are looking for a highly motivatedDFT / ATPG Engineer with 2+ years of experiencein SoC/ASIC test methodology, ATPG, scan and MBIST. The candidate should have strong hands-on expertise in DFT implementation on hierarchical designs and good experience with Tessent/Modus tools for ATPG, MBIST, and diagnosis.

  In addition to core DFT responsibilities, this role will also contribute toDFT automation flow development using Pythonand supportcontemporary AI-based technical initiatives internally within Microchip, aimed at improving productivity, debug efficiency, and overall flow quality.

  Key Responsibilities

• Develop and maintainPython-based automation flows and utilitiesfor DFT setup, pattern generation support, report parsing, coverage analysis, debug, and productivity improvement.
• Contribute toflow development and automation infrastructureto improve ATPG execution efficiency and methodology reuse across projects.
• Support and participate ininternal AI-driven technical initiativesrelated to DFT/ATPG automation, debug assistance, data analysis, and engineering productivity improvement within Microchip.
• HandleDFT implementation and support for hierarchical designs.
• Work onTessent/Modus ATPG flowfor DFT setup, pattern generation, validation, and coverage analysis.
• SupportTessent/Modus MBIST flowfor MBIST hardware generation and integration.
• UseTessent/Modus diagnosis toolsfor failure analysis and on-silicon debug.
• Performscan pattern simulation, debug, and pattern validation.
• SupportATPG pattern delivery to the Test Engineering / ATE team.
• Debugsimulation and DFT issues at block and SoC level.
• Collaborate withCAD, Design, STA, Product Engineering, and Test teamsto drive DFT solutions and new initiatives.

Requirements/Qualifications:

• 2+ years of experienceinDFT / ATPG engineering.
• Strong hands-on experience inscan pattern simulation and debug.
• Strong knowledge of Python scripting for automation, flow development, and methodology enhancement.
• Interest or exposure in applyingAI/ML-based engineering techniquesfor automation, debug, or data analysis is a plus.
• Good written and verbal communication skills.
• Hands-on expertise in handlingDFT on hierarchical designs.
• Strong experience withTessent and/or Cadence Modus ATPG toolsfor DFT setup and pattern generation.
• Experience withTessent/Modus MBIST toolsfor MBIST hardware generation.
• Experience withTessent/Modus diagnosis toolsfor on-silicon debug.

Preferred Skills

• Familiarity withPerl, Tcl, or Shell scriptingis a plus.
• Strong problem-solving and debugging skills.
• Self-motivated team player with the ability to work across cross-functional teams.