DV professional

Key Responsibilities:

• Develop and execute verification environments using OVM/UVM methodology (desirable).
• Write, simulate, and debug RTL using Verilog and SystemVerilog.
• Work with PLI/DPI interfaces, SystemC, or C/C++ for testbench and verification development.
• Develop test plans, test cases, and C/C++ based verification routines for IP and SoC verification across multiple generations.
• Perform coverage-driven verification and analyze functional coverage reports.
• Apply knowledge of system-level architecture including buses such as AXI and AHB.
• Understand low-power methodology, power architecture, and run/debug low-power scenarios.
• Utilize scripting languages such as Perl, Python, and shell for automation and testbench enhancements.
• Use linting tools and other verification utilities to ensure RTL quality and adherence to standards.
• Debug complex design and verification issues with excellent hands-on skills.
• Mentor junior engineers and support skill development within the verification team.
• Collaborate effectively with cross-functional international teams including digital and software design engineers.
• Knowledge of video/audio codecs is an added advantage.