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DV Engineer Gate Level Simulation

Randstad Sourceright
Fresher
Hyderabad, India
Early Applicant
  • Posted 8 days ago
  • Be among the first 10 applicants

Job Description

Position: DV Engineer – Gate Level Simulation (BB45FT RM 4354)

Key Skills

  • Hands-on experience in Design Verification (DV) with Gate Level Simulation.
  • Strong knowledge of SPICE, Verilog, SDF back-annotation, STA, and timing analysis.
  • Experience with netlist simulation, timing libraries, timing arcs, and latch-based designs.
  • Debug SDF annotation and gate-level simulation failures with root-cause analysis at gate/transistor level.
  • Experience in SPICE-to-gate-level correlation and what-if analysis.
  • Hands-on knowledge of SystemVerilog Assertions (SVA); UVM is a plus.
  • Strong debugging, analytical, and communication skills.

More Info

Job Type:
Permanent Job
Industry:
Other
Function:
Engineering
Employment Type:
Full time

Job ID: 153401345

Last Updated: 30-08-2026 07:54:25 AM
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