Digital Mixed Signal (DMS) Design Verification Engineer

B.Tech/M.Techwith2+years of industry experience inanalog/mixed signalbehavioral modelingat various levels of abstractionand full chip verificationusing these behavioral models & digital RTL/PA/Gates.

Good understanding of analog design concepts and mixed signal design architectures.Exposure toproducts that integrate a wide variety ofAnalog/Mixed-Signal/RFbuilding blocks such asPowerManagement,ADCs,DACs, PLL,bandgap references, oscillators, SerDesandrelated digitalcontrol and signal processing.

Hands on experienceindevelopingverificationplan,verificationenvironmentsandverification/debugofcomplexmixed signalproductsatblock &chip-top levels.

Exceptional interpersonal and communication skills,collaboratewith multipleteamsspread across the globeto get the work done.

Come up withverificationstrategyfor aproductafter going through product requirements and design specifications.

Createmodels foranalog/mixed-signalblocks for chip-top verification, tradeoffaccuracyvs.speed.Validate models againstactualdesign(self-checkingtests).

Create verification plans, buildverification environment, developself-checking testcases. Bring up chip topmixed-signalverificationenvironments (DMS DV).

Deploy industry standardSV/UVM basedmetric drivenverification approach.

Collaborate and work closelywith team members from various disciplines (system architects, digital design, analog design, digital DV, DFTetc.)for first pass silicon.

Support test and characterization teams in post-silicon validation.

CollaboratewithCAD teamto deploynext generationinnovativedesignverification methodologiesto reduceoverallTTM.

Modelling of analogblocks

SV-RNM

Familiarity withAnalog/Mixed-Signal/RFdesign architectures and debug experience with schematic capture tools such as Cadence Virtuoso and waveform viewers such as CadenceSimvision.

Experience and debug with digital simulators such as CadenceXcelium/Synopsys VCS.

Experience withSV/UVM (agent creation,env building, score-boarding, RAL etc.).

Tracking ofverificationmetrics(Vplan& Coverage)and regression management,Metric Driven Verification(MDV) frameworkusingtoolssuch asCadencevManager.

Experience withlanguages/tools/software relating toproductdevelopmentis an addedadvantage.

C

Automation with scripting languages: Python/Perl/Shelletc.