Digital Design Verification Lead

• Verification of complex designs such as accelerators/ datapath IP, processor core subsystems, complex interfaces/ protocols such as DDR/ Ethernet/ USB etc using leading edge methodologies like UVM Formal DV
• Create verification strategies and influence the decisions on methodologies to be adopted for the verification at block and sub-system level
• Architect the testbench and develop the verification environment in UVM and Formal based verification approaches
• Define testplan, tests and verification methodology for block / sub-system level verification. Work with design team in generating test-plans and closure of code and functional coverage.
• Integrate the block testbench at sub-system level UVM environment and verify integration. Interact with analog co-sim and firmware team in enabling toplevel chip verification aspects
• Package verification environment for Digital IP for seamless integration into verification flow at different stages of execution
• Technically mentor and lead a team of verification engineers
• Conduct detail-oriented DV reviews and drive adherence to quality metrics
• Evaluate 3rd party IPs on key qualitative aspects such as design quality, robustness of Design Verification (DV) practice, ease of DV environment integration and make recommendations. Establish evaluation flows for home-grown 3rd party IPs for consistent benchmarking of DV evaluation
• Build deep expertise on complex interfaces, peripherals protocols such as DDR, Ethernet, eMMC/ SD, MIPI, Display Port, HDMI, PCIe, high speed D2D
• Support post-silicon verification/ validation activities of the products working with design, product evaluation and applications engineering team
• Drive efforts towards development of Design Management and IP Centric infrastructure and flows across different tools such as Methodics / Perforce / Github / IP catalog creation etc
• Establish evaluation flows for home-grown 3rd party IPs for consistent benchmarking of evaluation
• Manage streamline efforts towards consolidation/ curation of digital IP blocks, such as standard peripherals, processor cores collaterals, high speed protocol interface IP
• Strive to remove complexity and ambiguity within the teams and their processes. Ability to distil and provide clear and actionable recommendations to the team

Position Requirements:

• Minimum B.E./ B.Tech/ M.Tech degree in Electrical/Electronics/Computer science
• 10+ years of experience in design verification with UVM and constrained random, coverage based verification approaches
• Strong understanding of DV concepts with an eye on developing scalable DV environment architecture that realizes first pass DV success
• Experience with translating Design Verification (DV) requirements such as test plans into a robust DV environment and generate coverage metrics for demonstrating DV convergence
• In-depth knowledge of Assertion based formal verification
• Adaptability to learn end application/systems and map into smart verification test plans
• Excellent debugging and analytical skills
• Good interpersonal, teamwork and communication skills to logically effectively drive discussions with teams spread geographically
• Understanding of standard on-chip interfaces such as APB/AHB/AXI/ Stream protocols is a strong plus
• Knowledge of Processor/SoC architecture and/or DSP fundamentals is a strong plus
• Experience with ASIC/ SoC product DV productization is very desirable
• Proven experience in managing/ handling large complex hardware projects in lead role
• Serve as the focal point for communications. Compile regular status updates for all stakeholders and effectively escalate critical issues and risks as necessary