DFX Engineer

Key Responsiblities

• Lead and define PHY specific Design for Test/Debug/Yield Features.
• Implementation of DFX features into RTL using verilog.
• Understanding of DFX Architectures and micro-architectures.
• Experience with JTAG (1149.1/1687/1500)/IJTAG, Scan Compression (EDT, SSH), and at-speed scan testing implementation.
• Gate level simulation using Synopsys VCS and Verdi.
• Spyglass bringup and analysis for scan readiness/test coverage gaps.
• MBIST planning, implementation, and verification.
• Support Test Engineering on planning, patterns, and debug.
• Support silicon bring-up and debug.
• Develop efficient DFx flows and methodology compatible with front end and physical design flows.
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Preferred Experience

• Experience with industry standard ATPG and DFx insertion CAD tools.
• Familiarity with industry standard DFX methodology: e.g Streaming Scan Network (aka SSN), IJTAG, ICL/PDL etc
• Familiarity with SystemVerilog and UVM.
• Fluent in RTL coding for DFx logic including lock-up latches, clock gates, and scan anchors.
• Understanding of low-power design flows such as power gating, multi-Vt and voltage scaling.
• Good understanding of high-performance, low-power design fundamentals.
• Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware.
• Exposure to post-silicon testing and tester pattern debug are major assets.
• Strong problem solving and debug skills across various levels of design hierarchies.

Academic Credentials

• BS/MS/PhD in EE/ECE/CE/CS with industry experience in advanced DFx techniques.