DFT Manager
DFT Manager
Broadcom10-12 Years
- Posted 3 hours ago
- Be among the first 10 applicants
Job Description
Job Description:
DFT manager is expected to manage and technically guide a high-performing DFT team focused on various ASIC engagements. DFT manager shall also be required to execute certain DFT critical tasks. As a part of the profile, DFT manager shall define chip-level testing plans, including Scan, MBIST, IO/IP tests.
Should be able to Collaborate with physical design, verification, and manufacturing teams on optimal DFT architectures. Work with Automated Test Equipment (ATE) post-silicon to achieve test coverage, root cause failures and improve manufacturing yield.
Candidate is required to be proficient with industry tools like Siemens Tessent, Synopsys TestMAX, and SpyGlass DFT.
Bachelors along with 12+ years of related experience or Masters degree along with 10+ years of related experience would be needed.
R027037
DFT manager is expected to manage and technically guide a high-performing DFT team focused on various ASIC engagements. DFT manager shall also be required to execute certain DFT critical tasks. As a part of the profile, DFT manager shall define chip-level testing plans, including Scan, MBIST, IO/IP tests.
Should be able to Collaborate with physical design, verification, and manufacturing teams on optimal DFT architectures. Work with Automated Test Equipment (ATE) post-silicon to achieve test coverage, root cause failures and improve manufacturing yield.
Candidate is required to be proficient with industry tools like Siemens Tessent, Synopsys TestMAX, and SpyGlass DFT.
Bachelors along with 12+ years of related experience or Masters degree along with 10+ years of related experience would be needed.
R027037
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Key Skills
SpyGlass DFT
Siemens Tessent
Synopsys TestMAX
About Company
Skills:
shell scripting, Spyglass DFT, Memory Repair BIRA BISR circuitry, X86 CPU architecture and microarchitecture, JTAG Memory BIST, advanced process nodes and hierarchical DFT strategies, DFT Design and verification using RTL simulations and emulation, RTL Coding, timing constraints and DFT mode timing analysis
Skills:
Jtag, Perl, Python, Tcl, MBIST, Siemens Tessent, Synopsys TestMAX SMS, DFT protocols, iJTAG, IEEE 1687, SoC DFT architecture and design, Cadence Modus, EDA Tools, Scan Compression, IEEE 1149.1, LBIST
Skills:
DFT verification, DFT Insertion, ATE Pattern Development, DFT concepts, RTL lint tool, BSCAN, MBIST, ATPG Coverage Analysis, equivalence check, ATE support, spyglass, Scan, IJTAG, Netlist level Insertion