DFT Lead
DFT Lead
cortex consultants llc- Posted 2 months ago
- Be among the first 10 applicants
Job Description
Role : DFT Lead
Experiecne : 8-15years:
Notice Period : Immediate to 30 Days
Work Mode : 5 Days office
Job Describtion : -
What You'll Do
Experiecne : 8-15years:
Notice Period : Immediate to 30 Days
Work Mode : 5 Days office
Job Describtion : -
What You'll Do
- Lead the DFT team to deliver solutions across multiple ASIC projects.
- Oversee DFT architecture, planning, and verification processes.
- Collaborate with cross-functional teams to ensure smooth DFT integration.
- Review and optimize ATPG/MBIST/LBIST strategies.
- Initiate and drive methodology enhancements and automation.
- Manage project schedules, deliverables, and resources.
- Provide guidance, mentoring, and feedback to team members.
- Engage with clients on technical discussions and updates.
- Support post-silicon bring-up and pattern debug as needed.
- Expert in scan insertion, ATPG, MBIST, and test-mode integration.
- Experienced with industry-standard DFT/ATPG tools like Synopsys, Cadence.
- Proficient in RTL design, CDC, synthesis, and physical design flows.
- Proven leader in managing complex DFT programs.
- Strong problem-solving and communication skills.
- Background in silicon bring-up and production test is advantageous.
- Holds a degree in Electronics, Electrical, VLSI, or a related field.
More Info
About Company
Skills:
boundary scan , Jtag, Perl, Scripting Languages, Python, scan compression, Scan Insertion, DFT methodologies, memory BIST, test pattern generation, DFT tools, ATPG, Cadence Modus, Genus
Skills:
Jtag, Compression methodologies, Scan Insertion, ATPG, Synopsys Tessent, EDA Tools, MBIST, Cadence, DFT strategy architecture
Skills:
Dft
Skills:
System Verilog, Jtag, Uvm, GLS, MBIST, LEC, ATPG, Scan Architectures, VMM, IJTAG, DFX, Coverage, Dft
Skills:
occ, compression at core level, coverage analysis, DFT architecture, Memory-BIST, no-timing simulations, ATPG pattern generation, SSN architecture, timing simulations, Scan Insertion, clock architecture