Q
DFT Engineer
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- Posted 7 days ago
- Be among the first 30 applicants
Job Description
Strong EDA tools experience Tessent - Testkompress, SSN, IJTAG, Synopsys - Fusion compiler, Design Compiler. Scan/ATPG patterns & test flows development, EDT, SSN and SSH architecture understanding, IJTAG,EDT, TestKompress, simulation and verification flow and experience of working in DFX architecture of complex SOC Patterns re-targeting
Good if any AMD/Intel/Qualcomm experience
This is the requirement for CAD, FLOW and METHODOLOGY team. Hence strict requirement on scripting is required along with core skills.
More Info
Key Skills
test flows development
Patterns re-targeting
Synopsys - Fusion compiler
DFX architecture of complex SOC
Scan ATPG patterns
SSN
IJTAG
TestKompress simulation and verification flow
IJTAG EDT
Tessent - Testkompress
EDT SSN and SSH architecture
About Company
Skills:
logic bist , Unix, Jtag, Perl, Linux, Tcl, scan diagnostics, Verilog RTL, silicon debug, back-annotated gate level verification, Scan compression and insertion, ATPG, at-speed test, Memory BIST and repair scheme implementation, IJTAG, Fault Simulation
Skills:
Perl scripting, Delay Faults, Pattern Simulation, Siemens Tessent, Transition Faults, Synopsys TestMAX, Pattern Generation, DFT Compiler, Scan Insertion, DFT implementation, DFT DRC violations, ATPG, Cadence Modus, Stuck-at Faults
Skills:
Perl, Python, Tcl, DFT rule compliance, low-power DFT methodologies, Modus EDT, ATPG test patterns, clock gating, IEEE 1149.1 JTAG, DFT architecture, power domain testing, IEEE 1500 standards, scan compression techniques, IJTAG, scan insertion strategies
Skills:
Tcl Scripting, Perl, Dft, Gate level simulations, Zero delay Timing Delay simulations, PD flow knowledge, ATPG Pattern generation, Timing Formal verification, JTAG P1500 protocols, SCAN DRC Coverage debug, Scan Insertion
Skills:
bist , Test Execution, Functional Testing, Perl, Scripting Languages, Python, Tcl, Scan Insertion, digital design concepts, ATPG, test plan development, EDA Tools, MBIST implementation, Cadence, Mentor, Synopsys