Introduction
At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You'll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation. With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress.
Your Role And Responsibilities
We are seeking a hands-on engineer with strong expertise in Design-for-Test (DFT), specifically LBIST (Logic Built-In Self-Test), to drive silicon bring-up, debug, and validation of on-chip self-test features. The ideal candidate will play a key role in validating LBIST infrastructure, debugging test failures, and ensuring high-quality silicon test coverage across pre-silicon and post-silicon stages. This role bridges DFT design, validation, and silicon debug, focusing on ensuring robust LBIST functionality and high-quality defect screening. You will work closely across teams to deliver production-ready test solutions and efficient debug methodologies for complex SoCs.
Key Responsibilities
- Develop, execute, and maintain LBIST validation test programs and automation using C, Python, or scripting languages
- Contribute to silicon bring-up with a focus on LBIST enablement, debug, and test mode validation
- Configure and run LBIST patterns on silicon, emulation, or simulation platforms
- Debug LBIST failures including MISR mismatches, signature errors, and coverage gaps
- Analyze LBIST-related issues such as clocking constraints, reset sequencing, scan chain integrity, and power/IR-drop impacts during test
- Perform low-level debug involving scan shift/capture cycles and test controller behavior
- Analyze waveform data, trace dumps, test logs, and on-chip debug instrumentation
- Interpret Verilog RTL/netlist to debug LBIST logic, PRPG/MISR structures, test controllers, and scan architecture
- Collaborate with DFT, RTL, physical design, validation, and product engineering teams to resolve issues
- Support silicon characterization and yield improvement activities related to LBIST
Preferred Education
Master's Degree
Required Technical And Professional Expertise
- Strong understanding of DFT concepts, especially LBIST architecture (PRPG, MISR, scan chains, test controllers)
- Proficiency in C/Python or scripting for test development, automation, and debug
- Hands-on experience with silicon bring-up and debug in test modes
- Good understanding of scan-based testing, LBIST pattern generation, and signature analysis
- Experience debugging test failures due to clocking, reset, X-propagation, or IR-drop issues
- Ability to read and debug Verilog RTL/netlists for DFT logic
- Familiarity with chip internals (clock domains, resets, power domains, test modes)
- Experience with ATE/bench-level bring-up or lab validation setups
Preferred Technical And Professional Experience
- Experience with DFT tools (e.g., Tessent, Modus, DFTMAX, or equivalent LBIST toolchains)
- Exposure to ATPG, compression, and scan diagnostics techniques
- Experience in post-silicon debug or yield ramp support
- Knowledge of power-aware LBIST, clock gating impacts, and X-handling techniques
- Familiarity with emulation platforms or pre-silicon verification of DFT features
- Understanding of firmware-test interaction for test mode entry/exit
- Experience with debug infrastructure and on-chip observability tools
- Proficiency with version control tools like Git
- Experience with LBIST coverage analysis and improvement techniques
- Knowledge of multi-clock LBIST architectures and constraints handling
- Familiarity with automotive/safety standards (ISO 26262) related to LBIST
- Exposure to yield learning, RMA analysis, and failure diagnosis flows
