We are seeking a highly motivated DFT Engineer to join our dynamic Hardware team. You'll be part of a great team of engineering professionals involved in the development, validation, and delivery of DFT (Design-for-Test) patterns for IBM's cutting-edge microprocessor chip design team.
Your Role and Responsibilities
As a member of the functional DFT team (Power on Reset, Architecture Verification Program, Array BIST teams), your responsibilities will include, but are not restricted to:
- Pattern generation.
- Simulation.
- Validation.
- Characterization.
- Delivery to Test Automation Engineers (TAE).
- Supporting IBM's Hardware Bring-up and Silicon Debug.
Required Education
Preferred Education
Required Technical and Professional Expertise
- 5-9 years of experience in DFT on complex designs, including:
- Scan insertion.
- Compression.
- MBIST (Memory Built-In Self-Test).
- ATPG (Automatic Test Pattern Generation).
- Simulations.
- IP integration and validation.
- Proven expertise in analyzing and resolving DRCs/TSVs.
- Hands-on experience in pattern generation for various fault models, pattern retargeting, and debugging techniques to address low coverage issues.
- Hands-on experience with Gate-Level DFT verification, both with and without timing annotations.
- Well-versed with industry-standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary Scan, LBIST, and STA constraint delivery.
- Hands-on experience with industry-standard tools used for DFT features.
- Proficiency in scripting languages such as TCL, Perl, or Python to automate design and testing tasks.
- Experience working with cross-functional teams like design, STA, and tester teams to ensure top quality DFT deliverables and DFT support and hand-offs.
- Excellent analytical and problem-solving skills, with a keen attention to detail.
- Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams.
- Fundamentals in microcontroller architecture, embedded firmware, functional verification, and RTL design.
- Experience working with ATE engineers for silicon bring-up, silicon debug, and validation.
- Experience in processor flow and post-silicon validation.
Preferred Technical and Professional Experience
- Experience developing automated testing.
- Experience with Ansible, Puppet, Chef, or other infrastructure configuration platforms.
- Knowledge of networking concepts and network devices.
