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Dear,
I hope you are doing well! My name is Uma from the TA team at Harman, and I'm reaching out to you today to briefly introduce myself as well as personally extend this invitation to you on behalf of my company.
Currently, we are looking to identify/invite exceptional talent like yourself, to join our Technical team at Harman.
About the Role
Job Description:
6 + Yrs Experience in MBIST , scan insertion, DRC analysis and DRC resolving , ATPG and simulations for Asics.
Test coverage improvement and Hierarchial test knowledge
Good debugging skills
Hands-on experience with Synopsys tools - TestMax Manager/ TestMax Atpg/ TestMax Advisor/VCS
Qualifications
Required Skills
If Sounds interesting please share your resume ASAP to [Confidential Information] with below details,
Regards,
Uma
Talent Acquisition Specialist
[HIDDEN TEXT]
Job ID: 128880579
Skills:
Jasper, Perl, Verilog, Debugging, Python, Tcl, Xcelium, Memory Test methodologies, Modus, Scan Insertion, VHDL, ATPG, Genus, silicon bring-up
Skills:
Vcs, ATE patterns, Scan Insertion, JTAG protocols, Tessent, Gate level simulation, ATPG, Post-silicon validation, P1687, TestMax, TetraMax
Skills:
Spi, Verilog, I2c, System Verilog, Scan Insertion, Digital DFT design, Logicbist, Mentor, Cadence, TetraMax, Gate level simulations, Synthesis, AMBA, ATPG, Digital RTL coding, Timing Constraints, Synopsys, PMIC
Skills:
Soc Architecture, Tcl, Python, Perl, HDLs, MBIST, ATPG flow implementation, UPF, Cadence digital implementation tools, DFT architecture definition, Tempus, CPF, Scan, Genus, tessent DFT, JTAG boundary scan
Skills:
boundary scan , Vcs, System Verilog, Memory BIST, JTAG protocols, ATPG, Logic Equivalency checking, Scan and BIST architectures, Gate level simulation debugging