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Title- DFT Engineer
Experience- 5+
Location- Bangalore
Key Responsibilities
• Define and implement DFT strategies including Scan Insertion, ATPG, MBIST/BIST, Boundary Scan, and JTAG.
• Collaborate with RTL, Verification, Physical Design, and STA teams for seamless DFT integration
• Develop and validate test plans, test infrastructure, and test patterns
• Perform ATPG, coverage analysis, and fault diagnosis
• Support silicon bring-up, debug test failures, and drive yield improvement
• Ensure DFT implementation meets manufacturing and DFM constraints
• Document DFT flows, architectures, and scripts; mentor junior engineers as needed.
Key Skills (Must-Have)
Strong hands-on experience in DFT / SoC Test Design
Expertise in Scan Insertion, ATPG, MBIST/BIST, Boundary Scan, JTAG
Experience with EDA DFT tools (Synopsys / Siemens / Cadence)
Good understanding of RTL (Verilog/SystemVerilog) and ASIC/SoC flows
Exposure to DFT-GLS, coverage analysis, and post-silicon debug
Scripting skills (Python / Perl / TCL) are a plus
Job ID: 137443523
Skills:
Vcs, Static Timing Analysis, Scan Insertion, Post-silicon validation, P1687, TetraMax, ATE patterns, JTAG protocols, ATPG, Gate level simulation, Tessent tool sets, TestMax
Skills:
Vcs, Static Timing Analysis, ATPG tools, Verdi, DFT ATPG, FSDB, Debug skills, Scripting skills, Timing Closure, Synopsys Tetramax, Scan Patterns, Mentor Graphics, Siemens, ATPG scripts
Skills:
boundary scan , Perforce, Git, Jtag, Perl, Tcl, Verilog Hdl, Synopsys SMS SHS flow, Mentor, Cadence, MBIST, Siemens Tessent, Shell flow, AT-Speed SCAN, Dft, IO BIST, ATE silicon debug, ATPG, EDA Tools, Stuck-AT, Synopsys, IJTAG
Skills:
boundary scan , Jtag, Perl, Python, Tcl, MBIST, Siemens Tessent, Insertion Coverage Analysis, Static Verification, Synopsys TestMAX, TetraMax, Cadence Modus, ATPG, Scan Compression, DRC Rule Checks, LBIST, EDA Tool Proficiency, DFT Architecture
Skills:
Vcs, ATE patterns, Scan Insertion, JTAG protocols, ATPG, Post-silicon validation, Tessent tool sets, P1687, TestMax, TetraMax, Gate level simulation debugging
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