DFT Engineer
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Title- DFT Engineer
Experience- 5+
Location- Bangalore
Key Responsibilities
• Define and implement DFT strategies including Scan Insertion, ATPG, MBIST/BIST, Boundary Scan, and JTAG.
• Collaborate with RTL, Verification, Physical Design, and STA teams for seamless DFT integration
• Develop and validate test plans, test infrastructure, and test patterns
• Perform ATPG, coverage analysis, and fault diagnosis
• Support silicon bring-up, debug test failures, and drive yield improvement
• Ensure DFT implementation meets manufacturing and DFM constraints
• Document DFT flows, architectures, and scripts; mentor junior engineers as needed.
Key Skills (Must-Have)
Strong hands-on experience in DFT / SoC Test Design
Expertise in Scan Insertion, ATPG, MBIST/BIST, Boundary Scan, JTAG
Experience with EDA DFT tools (Synopsys / Siemens / Cadence)
Good understanding of RTL (Verilog/SystemVerilog) and ASIC/SoC flows
Exposure to DFT-GLS, coverage analysis, and post-silicon debug
Scripting skills (Python / Perl / TCL) are a plus
Job ID: 137443523
Skills:
boundary scan standards, scan chain insertion and optimization techniques
Skills:
Jasper, Perl, Verilog, Debugging, Python, Tcl, Xcelium, Memory Test methodologies, Modus, Scan Insertion, VHDL, ATPG, Genus, silicon bring-up
Skills:
Vcs, ATE patterns, Scan Insertion, JTAG protocols, Tessent, Gate level simulation, ATPG, Post-silicon validation, P1687, TestMax, TetraMax
Skills:
Spi, Verilog, I2c, System Verilog, Scan Insertion, Digital DFT design, Logicbist, Mentor, Cadence, TetraMax, Gate level simulations, Synthesis, AMBA, ATPG, Digital RTL coding, Timing Constraints, Synopsys, PMIC
Skills:
Soc Architecture, Tcl, Python, Perl, HDLs, MBIST, ATPG flow implementation, UPF, Cadence digital implementation tools, DFT architecture definition, Tempus, CPF, Scan, Genus, tessent DFT, JTAG boundary scan
