DFT Design Verification Manager

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DFT Design Verification Engineering Manager

MANAGER SILICON DESIGN ENGINEERING

THE ROLE:

We are looking for an adaptive, self-motivated DFT design verification engineering manager to join our growing team. In this role, you will be leading a team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The NBIO DFx team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

THE PERSON:

As an Engineering Manager for the NBIO DFx India team, you will lead a team of skilled verification engineers in developing and executing DFT verification strategies for AMD's NBIO IP organization. You will be responsible for team leadership, project delivery, technical guidance, and cross-functional coordination to ensure first-pass silicon success for next-generation AMD CPUs, GPUs, and APUs.

KEY RESPONSIBILITIES:

• Design verification of High-Speed IO IP DFT features (e.g., JTAG 1149.x, IJTAG, MBIST, Scan, PRBS, IO Loopback, etc.)
• Lead and manage a team of design verification engineers, providing technical direction, mentorship, and performance feedback
• Define and drive verification strategy for DFT features, ensuring alignment with architectural goals, schedule, and quality targets
• Oversee test plan creation, review, and execution for block- and system-level verification
• Collaborate with design, architecture, and ATE engineering teams to resolve complex technical issues and optimize verification approaches
• Prioritize and allocate resources across multiple verification tasks and projects, balancing execution speed with quality

• Provide technical support to SoC and Post-Si teams to ensure successful bring up and enhance yield learning

PREFERRED EXPERIENCE:

• Proven track record of leading ASIC or SoC design verification teams through successful product tape-outs
• Strong expertise in SystemVerilog, UVM, C++ and coverage-driven verification methodologies
• Deep understanding of computer architecture, digital logic design
• Hands-on experience with EDA tools (Synopsys VCS, Verdi)
• Debugging and problem-solving skills for complex, multi-clock domain designs
• Strong people management and communication skills to drive geographically distributed projects
• Debug test failures to determine the root cause work with design engineers to resolve design defects and correct any test issues
• Experience with ATE (Automatic Test Equipment) - ATE test pattern & test flow development, debug, test, and characterization
• Design verification experience of High-Speed IO PHY and Controller logic is preferred

ACADEMIC CREDENTIALS:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field preferred

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Benefits offered are described: .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's Responsible AI Policy is available

This posting is for an existing vacancy.