DFT DESIGN ENGINEER

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DFT DESIGN ENGINEER

THE ROLE:

Test Development team is seeking a Silicon Design Engineer to have an exciting career on Scan, MBIST, iJTAG test development of latest 7nm MPSoC (Multi Processor System on Chip) products and beyond. The IPs range from ARM based Processor to critical IPs which provide automotive, data centre, machine learning and high-speed communication solutions. You will drive the Scan and MBIST teams for final pattern delivery to ATE, also expected to work closely with designers to make sure DFT structures are correctly inserted, with test engineers to make sure ATE test programs can be generated from the DFT (ATPG, MBIST) tools, with product engineers to make sure scan/mbist production test can run seamlessly and stable, and with yield engineers to debug and root-cause failures/defects. You will also be creating RTL design utilizing FPGA fabric resources to build communication logic for stimulus and response delivery between device and ATE.

THE PERSON:

Demonstrate a strong interest in digital design, DFT and post-silicon debug. Exhibit effective teamwork and communication skills collaborating across multiple sites and time zones. Possess strong analytical and problem-solving abilities, with a proactive approach to learning and tackling new challenges

KEY RESPONSIBILITIES:

• Work closely with design team and make sure DFT structures are correctly inserted.
• Developing, implementing and verifying DFT schemes (Scan/MBIST) on hard-IPs in FPGAs.
• Generating and Verifying ATPG patterns to test digital logic using Scan Compression and all types of fault models
• Generating and Verifying MBIST patterns
• Debugging pattern issues on Bench/ATE to root cause the problem
• Contribute to test coverage analysis and cost reduction through effective pattern development and post-silicon support.
• Apply expertise in DFT tools and scan testing techniques to assist in Diagnosis and Yield enhancement through Product lifecycle
• Support Test Engineering with test planning, pattern development and debug
• Collaborate closely with the New Product Introduction and Test/Product teams to ensure timely delivery of robust test patterns
• Develop Firmware driven cost-effective test strategies/methodologies with built-in diagnosis capability to enable efficient debugging and fault isolation on bench/ATE

PREFERRED EXPERIENCE:

• Experience with scan stitching and strong understanding of scan-stitching concepts
• Knowledge of fault models including stuck-at, transition, gate-exhaustive, path-delay, IDDQ, Bridge and Cell-Aware
• Exposure to post-silicon testing and tester pattern debug (major advantage)
• Experience with MBIST/BISR implementation and Tessent MBIST insertion flows
• Familiarity with DFT standards such as IEEE 1149.1/1149.6 for JTAG/BSCAN
• Strong hands-on ATPG experience and good understanding of ATPG inputs/outputs
• Experience with Tessent ATPG (Mentor) and Spyglass-DFT is a plus
• Strong debug skills and scripting capabilities
• Experience with automation scripts such as Python, Perl or TCL is a plus.

ACADEMIC CREDENTIALS:

• Bachelor's degree with 8+ years of experience or Master's degree with 6+ years of experience in Electronics Engineering or Computer Engineering preferred

LOCATION:

Hyderabad, India

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Benefits offered are described: .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.