Design Verification -Principal Engineer

Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > Hardware Engineering

General Summary

Minimum Qualifications

• 18+ Year of industry experiences in the following areas: Expertise in Synthesis - Synopsys Design Compiler, DCG/DC_NXT/Fusion Compiler and/or Cadence RC/Genus.
• Expertise on with multi-voltage, power aware synthesis, UPF flows in synthesis and low power designs.
• Expertise in formal verification with Cadence LEC/ Synopsys Formality
• Expertise in writing and debugging timing constraints
• Perl and/or TCL scripting, makefile flows.
  
  

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.
  
  

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.

We are looking for an experienced Principal Engineer – Design Verification to join our growing team in Noida. This is an excellent opportunity to work on cutting-edge semiconductor technologies and contribute to complex SoC/IP verification initiatives

• Key Requirements:
  
  

Strong expertise in Functional Verification, Power-Aware Verification, Formal Verification, and Performance Verification

Deep hands-on experience with UVM and SystemVerilog

Strong knowledge of Jasper or VC Formal for formal verification

Good understanding of UPF/CPF and PtPx methodologies

This role is ideal for seasoned verification professionals who are passionate about solving complex technical challenges and mentoring engineering teams while remaining deeply involved in execution.

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