Job Title: Design Verification Mid Senior Engineer (ASIC / SoC)
Level: Mid-Level
Experience: 6 - 10 Years
Location: Bengaluru
Employment Type: Full-time
Job Summary
We are looking for a
Design Verification Mid Senior Level Engineer with strong hands-on experience in
SystemVerilog and UVM to contribute to IP and SoC verification projects. The role focuses on building verification components, developing test cases, debugging complex failures, and achieving coverage goals in collaboration with senior engineers and design teams.
Key Responsibilities
- Develop and enhance UVM-based verification environments, including drivers, monitors, scoreboards, agents, and sequences
- Contribute to the creation and execution of verification plans based on design specifications and architecture documents
- Write directed and constrained-random test cases to validate functional correctness and corner cases
- Debug functional failures using waveforms, logs, and assertions, and work closely with design engineers for root-cause analysis
- Execute and analyze functional coverage and code coverage; identify and help close coverage gaps
- Run simulations, regressions, and coverage analysis using industry-standard EDA tools
- Participate in IP-level and SoC-level verification, including interface and protocol compliance testing
- Support code reviews, planning discussions, and internal technical training sessions
- Follow best practices for verification quality, reuse, and documentation
Required Qualifications
- B.E./B.Tech or M.E./M.Tech in Electronics, Electrical Engineering, or a related field
- 6-10 years of hands-on experience in Design Verification for ASIC/SoC projects
- Strong proficiency in SystemVerilog and UVM methodology
- Good understanding of digital design fundamentals and SoC architectures
- Experience with EDA simulators, regression management, and coverage tools
- Strong debugging, analytical, and problem-solving skills
- Effective communication and collaboration skills
Nice to Have
- Exposure to standard protocols (AMBA AXI/AHB/APB, PCIe, USB, etc.)
- Experience with low-power verification, assertions (SVA), or formal verification
- Prior experience working on reusable verification IPs
