Design Verification Lead - SoC/System Verilog

8-10 Years

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Early Applicant

Job Description

Responsibilities

Author verification plans from specs and micro-architecture; build reusable UVM environments from scratch at subsystem or SoC level.
Develop constrained-random and directed tests, scoreboards, checkers, coverage models, and assertions (SVA).
Drive coverage closure (functional, code, assertion), root-cause complex bugs, and work closely with RTL, architecture, and DFT.
Enable SoC-level verification including interface/IP integration, coherency, low-power modes, resets/boot, and performance validation.
Support silicon bring-up and correlation of failures to pre-silicon environments.

Must-have Qualifications

8+ years of hands-on ASIC verification experience (FPGA or emulation-only work does not count toward the 8 years).
Multiple production ASIC tapeouts with ownership of SoC or subsystem-level UVM environments and coverage closure.
Expert in SystemVerilog, UVM, SVA, and constrained-random methodologies; strong debug skills with waveforms and logs.
Experience verifying standard interfaces and complex subsystems (AXI/ACE, DDR/PCIe, coherency, memory/interrupt fabric, power states).
Strong testplanning, stimulus strategy, checkers/scoreboards, and closure discipline.

Nice To Have

Low-power verification (UPF-aware), performance/latency verification, firmware-aware verification, emulation acceleration as a complement to UVM.
Scripting (Python/Tcl) used to enhance hands-on verification, not in lieu of it.

Discounted / Not Counted Experience

Regression running/triage-only roles or lint/CDC-only roles are discounted.
IP-level-only verification without subsystem/SoC integration responsibility is insufficient.
Primarily management, methodology-only, or tool-maintenance roles without recent hands-on testbench development will be discounted.
FPGA-based validation experience does not count toward the minimum.

(ref:hirist.tech)