Design Verification Lead
Design Verification Lead
ALTEN Calsoft LabsThis job is no longer accepting applications
Job Description
Job Title: Design Verification Lead
Location: Bangalore/Hyderabad
Experience: 7+yrs
Job Type: Full-time
Industry: Semiconductors / VLSI / EDA
Education: B.E./B.Tech or M.E./M.Tech in ECE/EEE or related field
Job Description:
We are looking for a passionate and experienced Design Verification Lead to drive the verification of complex SoC/IP designs. The ideal candidate will have deep expertise in functional verification methodologies and will be responsible for managing a team, defining verification strategies, and ensuring high-quality silicon delivery.
Key Responsibilities:
- Own and lead verification activities for IP or SoC-level designs.
- Define and execute the verification plan, test strategy, and coverage goals.
- Develop and manage verification infrastructure (testbenches, stimulus, checkers, etc.).
- Collaborate with RTL design, DFT, PD, and firmware teams.
- Mentor and lead a team of verification engineers.
- Perform reviews of testbenches, test cases, and coverage reports.
- Drive simulation-based verification using SystemVerilog, UVM.
- Track and report project progress and debug issues independently.
- Participate in regression setup and continuous integration for verification.
- Deliver high-quality verified RTL to meet tape-out schedules.
Required Skills:
- 7+ years of experience in ASIC/FPGA verification.
- Strong expertise in SystemVerilog and UVM.
- Hands-on experience in developing complex verification environments.
- Good understanding of coverage-driven verification (functional and code).
- Experience with scripting languages (Perl/Python/Tcl).
- Knowledge of protocols like AXI, AHB, PCIe, USB, DDR, etc.
- Familiarity with formal verification is a plus.
- Strong debugging skills using waveform tools like DVE, VCS, or ModelSim.
- Prior experience in leading teams and driving project deliverables.
Good to Have:
- Experience in Emulation/FPGA prototyping.
- Exposure to low-power verification (UPF).
- Knowledge of verification IPs and reuse methodologies.
- Hands-on with gate-level simulations and performance verification.
Soft Skills:
- Excellent communication and interpersonal skills.
- Ability to lead and mentor junior engineers.
- Strong problem-solving and analytical thinking.
- Ability to work in cross-functional and global teams.
Interested can share CV to [Confidential Information]
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About Company
Skills:
Python, System Verilog, Systemc, Pcie, Hybrid test benches, MDV, DV signoffs, SV, CDV, Uvm, Simulation Scripts, test vectors, Coverage, Regression, UCIe, Axi, testplan creation, DV Infrastructure, building testbenches, stimulus based verification, SystemC based reference model
Skills:
shell scripting, Perl, Python, Tcl, mixed-signal design verification, Cadence Spectre simulation, Cadence Mixed-Signal Design Environment, SV UVM-based testbenches, VerilogAMS, behavioral modeling, systemverilog
Skills:
Fpga, Asa, Pcie, Technical Leadership, System Verilog, Uvm, Maxim GMSL protocol standard, USB 3, VIP development, FuSa verification, Effort and schedule estimation tracking, MIPI, AMS Verification, Grounds up verification environment development, TI FPD
Skills:
code coverage , Oops, Usb, Networking, Cpu, DDR, Pcie, Verilog, Ethernet, Arm, LINT, cdc, SV, SV METH, C tests, Axi, AMBA, spyglass, VHDL, SoC Verification, Graphics, RTL Coding, AHB
Skills:
Pcie, Systemc, Jenkins, Python, Perl, MATLAB, Design Verification, DV, Design Verification Lead, IP Verification, Subsystem Verification, systemverilog, Uvm, formal verification, Functional Verification, Constraint Random, Coverage Closure, Verification Plan, Specman E, Xcelium, Vmanager, Verilog-A, RNM, C Modelling, ISO 26262, Semiconductor, Pre-Silicon Verification