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• Strong expertise in SystemVerilog and UVM
• Experience in IP/SoC verification with any standard protocol (AMBA, PCIe, CHI, etc.)
• Hands-on in testbench development, debugging, and coverage closure
• Good understanding of verification methodologies and assertions (SVA)
• Strong problem-solving and debugging skills
Job ID: 145345975
Skills:
code coverage , perl, Regression Testing, Ovm, Ethernet Protocols, Python, multiple RTL simulators, X-propagation, Uvm, systemverilog, functional coverage
Skills:
scoreboard , System Verilog, verification environment, verification closure, script development, interface agents, Uvm, testbench components
Skills:
Usb, Fpga, Pcie, Perl, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, AMBA, formal verification, MIPI, Test Bench, transaction level modeling, AXI4
Skills:
Debugging, Perl, Python, Prototyping environments, Test plan development, Test bench infrastructure, Coverage driven verification, Uvm, systemverilog, Assertions, Directed constrained-random tests, RTL development environments, Emulation, Simulation
Skills:
test environments , scoreboard , C, Soc Architecture, Shell, Verilog, Test Cases, Sequencers, Mixed signal designs, Debugging RTL and Gate simulations, Industry-standard simulators, Agents, Verification testbenches, Revision control systems, Testbenches, Regression systems, Verification methodology, Directed and constrained random verification methodology, Monitors
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