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• Strong expertise in SystemVerilog and UVM
• Experience in IP/SoC verification with any standard protocol (AMBA, PCIe, CHI, etc.)
• Hands-on in testbench development, debugging, and coverage closure
• Good understanding of verification methodologies and assertions (SVA)
• Strong problem-solving and debugging skills
Job ID: 145345975
Skills:
test environments , scoreboard , C, Soc Architecture, Shell, Verilog, Test Cases, Sequencers, Mixed signal designs, Debugging RTL and Gate simulations, Industry-standard simulators, Agents, Verification testbenches, Revision control systems, Testbenches, Regression systems, Verification methodology, Directed and constrained random verification methodology, Monitors
Skills:
Debugging, Perl, Python, Prototyping environments, Test plan development, Test bench infrastructure, Coverage driven verification, Uvm, systemverilog, Assertions, Directed constrained-random tests, RTL development environments, Emulation, Simulation
Skills:
C, Python, System Verilog, Systemc, AI enabled DV development, Uvm
Skills:
Tcl Scripting, Python, System Verilog, HW–SW interaction, SoC TB architecture, test-plan creation, UPF-based methodologies, debug skills, UVM methodology, RTL integration, DV sign-off flows, gate-level simulation, power-aware verification
Skills:
Unix, Unix Shell Scripts, Perl, Python, make, Uvm, systemverilog
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