Design Verification Engineer
Design Verification Engineer
Quest GlobalThis job is no longer accepting applications
Job Description
Job Requirements
Job Title: Design Verification Engineer
We are seeking a skilled Design Verification Engineer to join our team.
The ideal candidate will have expertise in Verilog, System Verilog, UVM, and OVM with Min 3+ years of Experience.
If you have a strong background in verification methodologies and a passion for ensuring the quality of designs, we would love to hear from you. Apply now to be a part of our dynamic team.
Job Title: Design Verification Engineer
We are seeking a skilled Design Verification Engineer to join our team.
The ideal candidate will have expertise in Verilog, System Verilog, UVM, and OVM with Min 3+ years of Experience.
If you have a strong background in verification methodologies and a passion for ensuring the quality of designs, we would love to hear from you. Apply now to be a part of our dynamic team.
More Info
Key Skills
About Company
Skills:
Usb, Fpga, Pcie, Perl, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, MIPI, formal verification, AMBA, Test Bench, transaction level modeling, AXI4
Skills:
Shell, Perl, Python, Tcl, Cadence Xcelium, Mentor QuestaSim, PCI Express, Uvm, systemverilog, Synopsys VCS, Assertion-Based Verification, Constrained Random Verification, Functional Verification
Skills:
Perl, Python, Tcl, Functional Coverage, Uvm, SVA, systemverilog, ASIC SoC Subsystem IP verification
Skills:
Usb, DDR, Perl, Pcie, Ethernet, Python, Tcl, Uvm, coverage-driven verification, systemverilog, digital design RTL understanding, AMBA, MIPI, SVA
Skills:
Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV