Design Verification Engineer (PCIe)

Key Responsibilities & Skills:

* Perform functional and compliance verification of PCIe-based IPs and subsystems.

* Integrate and debug using Avery PCIe VIPs.

* Deep understanding of PCIe Gen4/Gen5 protocols.

* Expertise in SystemVerilog and UVM methodology.

* Strong debug skills with VCS, Questa, or Xcelium.

* Experience in coverage-driven and constraint-random verification.

* Hands-on with Python, Perl, or Shell scripting.

* Collaborate with design, validation, and architecture teams.

* Review test plans, reports, and coverage metrics.

* Excellent communication and problem-solving abilities.