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Job Summary:
We are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits
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Responsibilitie
es
Qualificatio
eam
Benef
Job ID: 150897413
Skills:
Ovm, Spi, Shell, Pcie, Verilog, I2c, Python, Usb, Can, Perl, Ethernet, Tcl, ARM Protocols, IP Verification, Uvm, GLS, Mipi, Emulation, Test bench model VIP development, dsi, LPDDR, CSI, SoC Verification, SV, AMs, LEC, Functional coverage, Axi, APB, AHB
Skills:
Jtag, Perl, Verilog, Python, System Verilog, Tcl, Mentor Questa, Cadence Xcelium, JasperGold, Uvm, Synopsys VCS, LP6, LP5, APB, CRI, DDR5, DDR4, IJTAG
Skills:
Low power simulations, Scripting knowledge in Python, Debugging gate level simulations, ARM based SoC, SV UVM based testbench development
Skills:
random testing , Oops, Pcie, Verilog, Debugging, System Verilog, FPGA verification, coverage assertions, Ethernet based protocols, VCS simulation flow, Otn, Uvm, VMM, AXI memory controllers, adversarial testing
Skills:
Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, System Verilog, Post-silicon debugging, CPU architecture, Verification flows, Rtl Design, Asic Design Verification, JTAG protocols, Digital Design, Debugging firmware, Assembly language programming
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