Design Verification Engineer

We are seeking a proficient ASIC/SoC Verification Engineer with over 5 years of experience to oversee a team of 23 engineers.

About the Role

The perfect candidate should possess extensive practical knowledge in GLS (Gate-Level Simulation), adept at constructing test-benches from the ground up in System Verilog (SV) and UVM.

Responsibilities

Excel in crafting verification plans and environments

Lead debugging processes

Provide mentorship to junior engineers

Exhibit top-notch communication skills

Demonstrate effective cross-functional collaboration abilities

Have test bench development experience with working on high speed protocols

Qualifications

Over 5 years of experience in ASIC/SoC Verification

Required Skills

Extensive practical knowledge in GLS (Gate-Level Simulation)

Proficiency in System Verilog (SV) and UVM

Preferred Skills

Experience in leading a team of engineers

Location: Bangalore/Ahmedabad/Pune/Hyderabad