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Strong experience in SystemVerilog and UVM
Solid understanding of SoC/IP verification methodologies
Good debugging and problem-solving skills
Develop and execute verification plans using SystemVerilog/UVM
Perform functional verification of SoC/IP components
Debug failures across simulation, emulation, and silicon
Work closely with design and DFT teams for testability and coverage
Analyze and validate test patterns (ATPG/ATE)
Support post-silicon validation and bring-up
Bachelor Of Technology (B.Tech/B.E)
Job ID: 151126831
Skills:
performance verification of ASICs, ASIC standard interfaces, verification components, formal tools, Design Verification, assertion-based verification, Uvm, systemverilog, memory system architecture
Skills:
DDR, Pcie, Ethernet, SRIO, RDMA, verification of ARM RISC-V based sub-systems or SoCs, IP or integration verification of high-speed interfaces, Design Verification, ROCE, RDMA TSO, automated flows and scripts for data exploration analysis and performance verification, 400G Mac, LRO, Congestion Control, waveform debugging tools, PSP, Simulators, SV Assertions, HBM, Formal Emulation, UVM based verification environments, RDMA over converged Ethernet
Skills:
cache coherency , Soc Architecture, DDR, Shell, Perl, Pcie, Ethernet, Python, Tcl, memory subsystems, Cadence Xcelium, checkers, Uvm, UCIe, coverage-driven verification, Assertions, systemverilog, Synopsys VCS, protocol compliance scoreboards, VIP integration, interrupts, SVA
Skills:
C, Python, low-power verification techniques, Design Verification, Uvm, systemverilog, co-simulation, SoC-level verification, formal verification methodologies, AI-assisted development tools, EDA Tools, ABV, HDL verification languages, SVA
Skills:
IP SoC verification, ASIC-SoC design verification, systemverilog
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