Design Verification Engineer
Design Verification Engineer
ALTEN Calsoft LabsEarly Applicant
- Posted 6 months ago
- Be among the first 10 applicants
Job Description
Design Verification Engineer - Senior / Lead / Sr. Lead
Job Description:
- Must have good knowledge on the verification flows.
- Excellent hands-on debug skills and problem solving attitude..
- Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC
- Experience of working on Functional Verification, SoC Verification, Emulation
- Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language.
- OVM/UVM Methodology knowledge and experience
- Must have good communication skills and the ability to work in a team environment.
- Preferably having experience in architecture such as x86 or ARM domain based SOCs
having SOC/IP performance verification background is added plus
Experience: 4 to 12 Years
Location: Bangalore / Hyderabad
Work Mode: Work from Office (WFO)
More Info
Job Type:
Industry:
Function:
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Key Skills
System Verilog PLI
DPI interface
About Company
Skills:
C, C++, Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, Post-silicon debugging, RTL design and verification flows, Simulation Tools, JTAG protocols, Digital Design, Assembly language programming
Skills:
Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog
Skills:
Debugging, Ovm, Verilog, System Verilog, Problem-solving skills, Functional Verification Coverage, Uvm, formal verification, DDR-PHY Design Verification, Design Verification of complex IPs, Low Power Verification, Gate Simulation
Skills:
Computer Architecture, C, Assembly Language, Vcs, Perl, Verilog, Python, System Verilog, Computer Engineering, Raven, UVM methodology, ACK, Microelectronics, Questa, Electrical Engineering
Skills:
Jtag, C, Verilog, System Verilog, Uvm, SOC RTL Design Verification