Design Verification Engineer

DV Engineer

Experience : 1-3 years

Location : Hyderabad

• Verilog, System verilog, UVM
• VHDL, UVVM
• 3rd party simulator exposure with VCS, Questa, Xcelium
• Proficient in simulation and HW languages
• Should be able to interpret various LRMs and comply with semantics and testcase creation.

Interested,please drop your updated resume to [Confidential Information]