Design Implementation (Synthesis) - Sr Eng/Lead/Staff

We are seeking an experienced individual to contribute to RTL, UPF, and Physical aware Synthesis for cutting-edge technology nodes. The role involves logic equivalence checking, scripting, and Netlist Timing Signoff.

Key Responsibilities

• Perform RTL, UPF & Physical aware Synthesis for cutting-edge technology nodes.
• Conduct logic equivalence checking.
• Implement scripting for design automation.
• Execute Netlist Timing Signoff.

Required Skills & Experience

• 3+ years of experience in RTL, UPF & Physical aware Synthesis, logic equivalence checking, scripting, and Netlist Timing Signoff.
• Proficiency in Python/Tcl.
• Familiarity with Synthesis tools (e.g., Fusion Compiler/Genus).
• Fair knowledge in LEC (Logic Equivalence Check) and LP (Low Power) signoff tools.
• Proficient in VLSI front-end design steps:
• Verilog/VHDL
• Synthesis
• QoR (Quality of Results) optimization
• Equivalence Checking
• Should be sincere, dedicated, and willing to take up new challenges.

Preferred Skills

• Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus.

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
• ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.