Position Overview
We are seeking an experienced DFT Engineer with strong expertise in Design-for-Test methodologies for complex ASIC/SoC designs. The ideal candidate will be responsible for implementing and validating DFT architectures to ensure high test coverage, manufacturability, and silicon quality for next-generation semiconductor products.
The role requires deep understanding of scan insertion, ATPG, MBIST, JTAG, compression techniques, and SoC-level DFT integration flows.
Key Responsibilities
- Define and implement DFT architecture for complex ASIC/SoC designs.
- Perform scan insertion, scan stitching, and DFT integration activities.
- Develop and validate DFT features including:
- Scan
- ATPG
- MBIST
- LBIST
- JTAG/Boundary Scan
- Test Compression
- Work on DFT verification and debug activities.
- Generate and analyse ATPG patterns and coverage reports.
- Collaborate closely with RTL Design, Physical Design, STA, and Validation teams.
- Support gate-level simulations and silicon bring-up activities.
- Drive DFT sign-off activities ensuring quality and test coverage targets are met.
- Analyze and resolve DFT-related timing and implementation issues.
- Participate in design reviews and provide DFT recommendations during architecture stages.
Requirements
Required Skills & Qualifications
- Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or related field.
- 6+ years of hands-on experience in DFT for ASIC/SoC designs.
Strong expertise in:
- Scan Insertion
- ATPG
- MBIST/LBIST
- JTAG
- Boundary Scan
- Compression Techniques
Good understanding of:
- RTL-to-GDSII flow
- Semiconductor test methodologies
- DFT verification
- Timing and physical constraints
- Experience with DFT tool flows from Synopses/Tessent/Cadence ecosystems.
- Strong debugging and problem-solving capabilities.
- Ability to work in fast-paced semiconductor product development environments.
Preferred Skills
- Experience with advanced technology nodes.
- Exposure to Full-Chip DFT integration.
- Knowledge of low-power DFT techniques.
- Familiarity with STA and Physical Design interactions.
- Experience with silicon debug and yield analysis.
- Exposure to Automotive, Networking, AI/ML, CPU/GPU, or High-Performance Compute SoCs.
Tools & Technologies
- Synopsys DFT Compiler
- Tessent
- Modus
- TetraMAX/TestMAX
- SpyGlass DFT
- VCS / Xcelium / Questa
- Verilog/SystemVerilog
- Perl / Python / Tcl
Key Competencies
- Strong DFT architecture and implementation expertise
- Analytical and debugging skills
- Understanding of semiconductor manufacturing test flows
- Cross-functional collaboration capabilities
- Ownership mindset and execution focus
- Attention to detail and quality-driven approach.
