Design Flow / Methodology Engineer (CAD)

About the Role

We are seeking an experienced Design Flow / Methodology Engineer to own the RTL-to-GDSII implementation flow and to define how AI automates it. You will build, qualify, and maintain the synthesis, place-and-route, timing, and physical signoff methodology that every project runs on, and you will turn that hands-on flow expertise into product. As with our verification roles, your domain judgment is the input: you build the automation because you have closed timing, debugged congestion, and driven tapeouts yourself. This is a founder-adjacent role with real ownership over methodology and tooling strategy. You will set the flow, not just run someone else's scripts. 

Responsibilities

• Own the end-to-end RTL-to-GDSII design flow: synthesis, floorplanning, place-and-route, clock tree synthesis, timing closure, and physical signoff

• Build, qualify, and maintain reusable flow infrastructure, scripts, and automation that scale across IPs, subsystems, and full-chip projects

• Drive timing, power, area, and congestion methodology, including static timing analysis (STA) setup, constraint development, and signoff correlation

• Integrate and qualify EDA tools and manage PDKs, standard cell libraries, IP, and technology files across nodes

• Own physical verification and signoff flows: DRC, LVS, antenna, EM/IR, and reliability checks

• Define and drive AI-assisted design flow automation: parameter tuning, flow orchestration, congestion and timing-closure assistance, and LLM-assisted methodology workflows. Your judgment determines what the product automates and how

• Partner with RTL, architecture, DV, infrastructure, and AI engineering, and represent implementation in cross-functional architecture decisions

• Set long-term flow, CAD, and tooling strategy 

Qualifications

• PhD in EE/CS/CE with 4+ years of physical design / design methodology / CAD experience, or MS with 7+ years
• Drove the implementation flow for at least one IP, subsystem, or SoC from netlist through tapeout
• Deep expertise across the RTL-to-GDSII flow: logic synthesis, place-and-route, clock tree synthesis, STA, and physical verification
• Hands-on with Synopsys, Cadence, and Siemens tools such as Design Compiler / Fusion Compiler, IC Compiler II, Genus, Innovus, PrimeTime, Tempus, StarRC, Calibre, ICV, or PVS
• Strong scripting and flow-automation skills with Tcl, Python, Perl, Bash, Makefiles, or CI/CDintegrated infrastructure
• Solid grounding in timing, power, clocking, and low-power methodology including UPF or CPF, multi-voltage, and multi-corner multi-mode signoff
• Working knowledge of PDKs, standard cell and memory libraries, IP integration, and physical signoff requirements 

Preferred Qualifications 

• Multiple tapeouts across advanced process nodes 
• Built reusable CAD or design-flow infrastructure at scale
• Experience with low-power, multi-voltage, or high-performance compute and AI accelerator implementation
• Familiarity with AI-assisted or ML-driven design flow automation and parameter optimization
• Exposure to high-speed protocols, security IPs, cache coherency systems, or large interconnect and NoC implementation
• Experience mentoring or leading implementation and CAD engineers 

What We're Looking For

• Ownership and execution at the level of someone who has driven implementation to tapeout

• Comfortable building flows from scratch in a fast-moving startup

• Works independently while staying close to the founding team

• Wants to define how AI changes physical design and methodology, not just use it

• Strong technical communication and the judgment to set methodology for a team