Design Engineering Architect

14-16 Years

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Early Applicant

Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Description:
Design Verification Leadership for IP development team.
B. Tech/M.Tech with 14+ years of relevant experience.
Position is based in Bangalore part of Cadence Silicon Solutions Group.
Verification role for Serial and Interface Design IPs verification (PCIe, CXL, UCIe,USB, Ethernet Protocols )
Define and implement verification strategies aligned with project goals, quality standards, and timelines.
Drive coverage-driven verification and ensure robust test plans for functional correctness.
Collaborate with architecture, design, and validation teams to ensure comprehensive verification closure.
Drive adoption of automation, regression strategies, and continuous integration for verification flows with AI usage.
Mentor a team of verification engineers, fostering technical growth and best practices.
Self-starter and learner with passion for on time delivery quality.
Strong problem solving, analytical and debug skills.
Excellent verbal and written communications skills for clear communication of Project status and risk mitigation plans etc.

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