Design Engineering Architech

Job description

-Design and implement DFT IP w/ Verilog/SystemVerilog and/or VHDL

- Design and implement RTL for DFT IP incl. POST, IST

- Develop synthesis automation for DFT IP including synthesis and timing constraints, RTL insertion and verification

- Own and maintain, extend, and enhance existing DFT IP like LBIST

Role: Technical Architect

Industry Type: IT Services & Consulting

Department: Engineering - Software & QA

Employment Type: Full Time, Permanent

Role Category: Software Development

Education

UG: Any Graduate

PG: Any Postgraduate

Key Skills

Design engineeringAutomationVHDLDFTVerilogManager TechnologySystem verilogRTL