Design Engineer II

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Role Overview:

Key Responsibilities:

• Verification Infrastructure:Simulation testbenches in C/C++/RTL and lead the development of reusable UVM environments.
• Advanced Verification:Champion the integration of formal verification, and AI-driven coverage analysis.
• Cross-Functional Collaboration:Partner with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements.

Required Qualifications:

• B.Tech/M.Tech in ECE with
• Experience inSystemVerilog/UVMandC/C++for architectural modeling.
• Experience with processor integration (e.g., RISC-V or ARM) and industry-standard protocols like AMBA/PCIe.
• Expertise in scripting (Perl, Python, or Tcl) for verification flow automation.
• Proven track record in verifying complex pipelines, memory subsystems, or ISA implementations.

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