CPU RTL Design Engineer (RISC-V, Microarchitecture)

CPU RTL Design Engineer (RISC-V, Microarchitecture)

Hiring: CPU RTL Design Engineers | Scaledge

We are looking for strong RTL Design Engineers to work on a RISC-V CPU core derived from an existing high-performance architecture. This is a great opportunity to contribute to CPU microarchitecture, pipeline design, and next-generation silicon development.

Responsibilities

• RTL design and enhancements across CPU pipeline stages: Fetch, Decode, Rename, Issue, Execute, Load/Store, Commit
• Pipeline control, hazard handling, and scheduling logic
• Caches, Memory Management, Exceptions, and Interrupts
• Microarchitecture alignment and design trade-offs
• Subsystem integration, RTL debug, and quality improvements
• Collaboration with architecture and verification teams

Requirements

• Strong Verilog/SystemVerilog RTL experience in CPU design
• CPU microarchitecture knowledge (RISC-V preferred)
• Experience with at least 1 tape out

Location: Bangalore/Ahmedabad/Pune/Bhubaneswar/Hyderabad/Noida

Experience: 4–12+ years

If you are passionate about CPU design and want to work on a cutting-edge architecture, let's connect.

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