Analyze and interpret transistor-level, gate-level, and memory circuit schematics to understand functionality, performance, and timing behavior.
Perform circuit simulations using industry-standard SPICE simulators, including DC, transient, and timing analysis.
Develop and validate building block and memory circuit designs through simulation, characterization, and correlation activities.
Debug gate-level simulation failures and perform detailed root-cause analysis at both gate and transistor levels.
Conduct what-if analysis and implement design modifications to validate corrective actions and optimize circuit performance.
Work with latch-based and sequential logic designs, ensuring compliance with timing requirements and design constraints.
Support timing characterization activities, including timing libraries, timing arcs, and associated file formats.
Execute and analyze netlist simulations using Verilog MOS switch-level models, including zero-delay, unit-delay, and path-delay simulation methodologies.
Correlate gate-level simulation results with SPICE simulations to ensure design accuracy and timing closure.
Collaborate closely with design, verification, and architecture teams to resolve complex circuit and timing issues.
Document findings and communicate technical concepts effectively to cross-functional engineering teams.
Required Qualifications
Strong experience with transistor-level and gate-level circuit analysis and debugging.
Hands-on expertise with SPICE simulation tools and circuit characterization methodologies.
Solid understanding of memory architectures, latch-based designs, and timing verification.
Experience with timing libraries, timing arcs, and characterization flows.
Proficiency in Verilog switch-level modeling and gate-level simulation environments.
Strong debugging skills with the ability to identify and resolve issues at both circuit and transistor levels.
Excellent analytical, problem-solving, and communication skills.
Preferred Qualifications
Experience with UVM-based verification environments.
Familiarity with advanced timing validation and silicon correlation methodologies.
Exposure to semiconductor design, verification, and post-silicon validation flows.
