Chip Top lead
Chip Top lead
Quest Global- Posted 3 months ago
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Job Description
Job Requirements
Role Overview
We are looking for an experienced Physical Design Chip Lead to lead the end-to-end implementation of complex SoCs/ASICs.
The candidate will be responsible for driving physical design activities, coordinating cross-functional teams, ensuring design closure, and meeting PPA (Power, Performance, Area) goals.
Key Responsibilities
Required Skills & Experience
Role Overview
We are looking for an experienced Physical Design Chip Lead to lead the end-to-end implementation of complex SoCs/ASICs.
The candidate will be responsible for driving physical design activities, coordinating cross-functional teams, ensuring design closure, and meeting PPA (Power, Performance, Area) goals.
Key Responsibilities
- Lead and own the full-chip physical design flow from RTL to GDSII.
- Drive floor planning, power planning, clock tree synthesis (CTS), placement, routing, and signoff (timing, IR-drop, EM, DRC/LVS).
- Coordinate with block-level PD owners and ensure seamless integration at the chip level.
- Analyse and optimize PPA to meet design targets.
- Collaborate with RTL, STA, power, DFT, verification, and package teams for design convergence.
- Lead ECO cycles for timing, congestion, and physical sign-off closure.
- Review and debug physical verification and timing issues.
- Manage schedules, resources, and risk tracking for PD deliverables.
- Prepare and present project status, risks, and mitigation plans to management and customers.
- Mentor and guide junior engineers in the team.
Required Skills & Experience
- 10+ years of experience in ASIC/SoC physical design with at least 3+ years in a lead role.
- Strong expertise in industry-standard PD tools (Cadence Innovus, Synopsys ICC2, etc.).
- Proven experience in full-chip integration and signoff flows.
- Good understanding of STA (PrimeTime), physical verification (Calibre), and low-power design methodologies (UPF/CPF).
- Hands-on experience with process nodes (22nm / 28nm preferred).
- Strong debugging and problem-solving skills in timing, congestion, and physical verification.
- Familiarity with package/chip co-design and IO planning.
- Hands on experience in handling Analog custom routes, understanding the spec to meet R and C
- Good hands on experience in Full chip CTS implementation
- Good hands on experience in IO Ring creation, Partitioning, Timing budgeting, VA creation ( Design Planing activities )
- Experience in multi-voltage, multi-frequency design
- Knowledge of EM/IR-drop analysis and mitigation techniques.
- Excellent communication and leadership skills.
More Info
Key Skills
physical verification Calibre
STA PrimeTime
Analog custom routes
multi-frequency design
package chip co-design
Cadence Innovus
VA creation
IO Ring creation
Full chip CTS implementation
EM IR-drop analysis
mitigation techniques
Synopsys ICC2
Timing budgeting
IO planning
signoff flows
low-power design methodologies UPF CPF
full-chip integration
About Company
Skills:
Verilog, Perforce, Git, Clock reset domain design, SoC integration, systemverilog, Design Compiler, RDC tools, UPF, spyglass, Axi, APB, BUS Protocols, Genus, Questa, Lint tools, Synthesis awareness, CPF, AHB, Low-power design