CAD Engineer

Seeking motivated CAD engineer

• Supporting product and test chip PG's across various technologies at TI

• Supporting Scribe Layout (KERF) Development and Support across various process nodes

Job description:

• Conversion of product or technology development test chip layouts (LAFF, GDS) into fracture data

• Preparing mask orders for shipment to vendors and managing the integrity and archival of data that is generated through this process. (Mask Data Preparation)

• Development and Support of Tech/fab-specific scribe recipe development & maintenance to generate reticle floorplan databases

• Drive design and development of new software tools, scripts, automation and interfaces for use in the PG/Tapeout process.

• Collaborate with & guide various teams within Advanced Technology Development (process development, PDK), EDA and business units to ensure the necessary information is available to complete the PG process.

• Ensure consistent application of methodologies and best practices

Required Key Skills

o Understanding of Layout and basics of fabrication process (FEOL/BEOL)

o Knowledge of Mask data tools like Cadence Virtuoso, (Pegasus designrev / Mentor calibredrv

o Maintain a high standard for cycle time and quality

o Excellent scripting skills with atleast one of PERL, Python, TCL and Cadence skill with special focus on layout automation and geometry processing algorithms

Nice to have:

o Knowledge of Scribe, KERF, Reticle development

o Understanding of ETEST structures, fab alignment structures and photolithography

o Understanding of Physical Verification signoff (DRC) and runset flow

o Mask Data Preparation tools like Cadence Mask Compose

Educational Qualifications

Bachelor's degree in Computer Science, Electrical/Electronic Engineering or related field with (2-6) years of Hardware Engineering or related work experience.