What You'll Be Doing:
- Defining and developing ASIC RTL verification at both chip and block levels.
- Creating and executing verification plans for complex digital designs, particularly focusing on PCIe/CXL protocols.
- Collaborating with cross-functional teams to ensure seamless integration and functionality of designs.
- Utilizing advanced verification methodologies and tools to achieve high-quality results.
- Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement.
- Communicating with internal and external stakeholders to align on project goals and deliverables.
The Impact You Will Have:
- Enhancing the reliability and performance of Synopsys digital verification processes.
- Improving time-to-market for robust Synopsys Interface IP controller through efficient verification methodologies.
- Mentoring and nurturing a highly skilled verification team, elevating overall project quality.
- Influencing strategic decisions that shape the future of Synopsys capabilities.
- Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements.
What You'll Need:
- Extensive experience in ASIC RTL verification.
- In-depth knowledge of PCIe, CXL , UCIe and similar IO protocols.
- Proficiency in advanced digital design verification tools and methodologies.
- Strong problem-solving skills and the ability to work independently.
- Excellent communication skills for effective collaboration with diverse teams.
- Experience of 15+ years in relevant domain.
Who You Are:
- A mentor who fosters talent and encourages innovation.
- A proactive problem solver who thrives in complex environments.
- An effective communicator with the ability to convey technical concepts to a broad audience.
- A team player who values collaboration and diversity.
