ASIC RTL Design Technical Leader | RTL, System Design, Micro Architecture, Datapath

Meet the Team

Come join us and be part of the Cisco SiliconOne team and take part in crafting Cisco's groundbreaking Enterprise and Service Provider solutions by crafting some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a rare combination of a startup culture with the benefits of working for the top tier networking company in the world!

Your Impact

Cisco SiliconOne team is looking for an expert and talented ASIC Engineering Technical Leader. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products.

• Architectural work: In-depth understanding of the architecture, and identification of problems and solutions. Oversees the definition, architecture and design, in addition to making design decisions.
• Drives design solutions across the business. Ensure culture of code reviews and postmortems.
• All aspects of implementation: Specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for low power and area; highlighting issues and standard methodologies for power and area optimization.
• Review complex designs and makes recommendations for improvements.
• Creates guidelines and standards.
• Document and improve standard methodologies to make product successful.

Minimum Qualifications

• BS/MS and 12+/10+ years respectively of hands-on experience in large-scale, high-performance ASIC.
• Architecture and implementation specification creation.
• RTL development (Verilog, SystemVerilog, VCS, Spyglass, CDC, Formal verification)
• Experienced in system debug and SW/HW bring-up, system validation of silicon towards FCS.
• Gate-level understanding of RTL and Synthesis
• Programming/scripting skills (C, C++, Perl)
• Hardware Emulation Platforms and tools (such as EVE, Veloce)
• Good written/verbal interpersonal skills and leadership skills.

Preferred Qualifications

• Worked in architecture and definition of high-scale, high-performance ASICs.
• Planning overall domain architecture strategy and defining the requirements.
• Conducting & leading various architecture reviews.
• Driving complex debugs and system level integration aspects
• Valid experience in implementation: specification, RTL design, lint, cdc, timing analysis, formal verification, system testing.
• Valid experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team.
• Mentoring the senior resources in the team on architectural and design strategies.
• Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion.
• Excellent communication skills both verbal and written

Why Cisco

At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.