ASIC RTL Design Engineer

Proxelera is a fast-growing, 4-year-old semiconductor and high-tech engineering company, delivering cutting-edge solutions across architecture, design, verification, and analytics. We work on globally recognized projects with leading customers across US & APAC. We are currently hiring immediate VLSI experts for our client, ODC and Turnkey projects.

Job Title: RTL Design Engineer

Experience: 510 Years | Location: Bangalore (Proxelera Office)

Job Description:

• Experience in coding RTL blocks and/or algorithms for ASICs in Verilog/SV in at least 2 projects is mandatory. This candidate could also have worked on a few RTL integration projects, but at least 2 RTL development (coding) projects are needed.
• Experience in running QC checks (CDC, Lint, X-prop) on the design and cleaning up design issues is mandatory
• One or two FPGA RTL projects are OK, but the remaining projects must be ASIC RTL projects
• Synthesis and constraint writing experience is good to have, but not mandatory

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