ASIC Physical Design Engineer

PIMIC is building the compiler that brings Processing-in-Memory AI to life.

InCommon is hiring on behalf of a California based company that is building ultra-low-power neural processing technology for edge AI — chips that run advanced AI workloads within tight power and memory budgets. The Processing-in-Memory (PIM) architecture computes directly inside memory, breaking the traditional bottleneck of shuttling data back and forth.

Role : VLSI Physical Design Engineer

India-based · Remote

5+ years, hands-on | Full -time

B.S. in Electrical Engineering

Requirements:

• 5+ years hands-on SoC/ASIC physical design, owning the full flow: floorplanning → place & route → CTS → routing → ECO → timing closure → physical verification → signoff → tapeout
• Advanced-node tapeout experience — ideally 7nm, 12nm, 22nm
• Extensive hands-on Cadence Innovus (P&R, physical optimization, CTS, routing, ECO)
• Timing closure across multiple modes and PVT corners using PrimeTime or Tempus with MMMC methodology
• UPF low-power design flow from synthesis through P&R — able to develop and debug UPF from RTL power-domain specs and power intent
• Strong Tcl scripting, plus at least one of Python / Perl / shell
• B.S. in Electrical Engineering

Strongly preferred

• Multiple successful SoC/ASIC tapeouts at 12nm, including full chip-level ownership
• Hierarchical and flat physical design methodologies
• Complex multi-voltage, multi-power-domain SoCs
• High-speed interface experience (PCIe or other complex IP)
• Mixed-signal integration — signal/noise isolation, analog-digital power isolation, impedance matching, differential routing
• Familiarity with DFT, scan, CDC/reset, package constraints, bump planning, wirebond, WLCSP, or flip-chip
• RTL expertise
• Experience using AI/agentic tooling to cut design-cycle time and reduce errors

What you'll do

• Own the complete SoC physical design flow, from netlist and UPF handoff through floorplanning, placement, CTS, routing, ECO, timing closure, physical verification, signoff, and tapeout.
• Perform chip- and block-level floorplanning, macro placement, I/O and pin planning, power-domain planning, power-grid design, congestion analysis, and routing-resource planning.
• Drive place and route, physical optimization, CTS, routing, and ECO implementation in Cadence Innovus.
• Close timing across multiple modes and PVT corners using PrimeTime or Tempus (MMMC).
• Set up, run, debug, and close Calibre LVS, DRC, antenna, wirebond, and WLCSP checks; interpret foundry rules and implement manual or automated fixes in Innovus.
• Run RC extraction (Quantus) and IR-drop / electromigration analysis (Voltus).
• Perform RTL- and gate-level power analysis (Joules).
• Collaborate with RTL and verification engineers, using Xcelium or VCS waveforms to debug logic, timing, and integration issues.
• Participate in tapeout readiness reviews and ensure timing, physical verification, power integrity, low-power, and foundry signoff requirements are complete.
• Use AI responsibly to find solutions that save cycle time and reduce human error.

Who thrives here

Highly hands-on, detail-oriented, and technically rigorous. Able to independently troubleshoot difficult design and signoff problems with minimal supervision. Strong ownership mindset — drives assigned blocks or chip-level responsibilities through to closure. A clear communicator who works well across front-end, verification, DFT, package, CAD, and foundry teams, and who's comfortable prioritizing multiple closure issues under schedule pressure.

Why this role

Small, fast-moving team building genuinely novel silicon. Real ownership from day one.