ASIC Engineer Intern, Physical Design
- Posted 3 days ago
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Job Description
Meta is seeking an ASIC Engineer Intern to join our Infrastructure organization. Our servers and data centers are the foundation upon which our rapidly scaling infrastructure efficiently operates and upon which our innovative services are delivered. By holding this role, you will be an integral member of an ASIC team to build accelerators for some of our top workloads enabling our data centers to scale efficiently. You will have an opportunity to participate in design implementation, physical design, and design power estimation/management using state of the art tools. Come work and learn alongside our expert ASIC engineers to build Green data center accelerators.Internships are twelve (12) to sixteen (16) weeks long.
ASIC Engineer Intern, Physical Design Responsibilities:
Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.
ASIC Engineer Intern, Physical Design Responsibilities:
- Participate in Design Implementation, Physical Design, and Design Power activities and provide feedback.
- Contribute to optimizing RTL for some of the IPs to achieve best in class PPA (Power, Performance, Area), and support implementation and physical design of the same.
- Contribute to develop unique recipes to achieve the best PPA using various physical design strategies.
- Develop scripts, tools, and methods to enhance PPA (Power, Performance, Area).
- Support and develop EDA Infrastructure, and help improve designer productivity.
- Currently has, or is in the process of obtaining, a Bachelor's degree in Electrical Engineering, Computer Engineering or related engineering fields
- Knowledge of Computer Architecture , Logic Design and Device Physics fundamentals
- Knowledge of Verilog, System verilog
- Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment
- Intent to return to degree-program after the completion of the internship
- Currently has, or is in the process of obtaining, a Masters or PhD degree in Electrical Engineering, Computer Engineering or related engineering fields
- Experience with Synthesis and Physical Design flows and methodologies
- Scripting capability with TCL and Python
- Experience with High Performance Computing
- Experience with Digital Design Techniques
- Creativity and problem solving capabilities
Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.
More Info
Key Skills
Synthesis and Physical Design flows
Digital Design Techniques
About Company
Skills:
Python, Tcl, floorplanning, Physical design flows, Clock CTS, Logical Equivalence, Synthesis, Timing Analysis, EDA Tools, Budgeting, Physical Verification DRC LVS ERC, Place And Route
Skills:
Computer Architecture, Logic Design, Perl, Verilog, Python, LINT, high performance computing, Digital Signal Processing Techniques, HLS, Synthesis, VHDL, Physical Design tools
Skills:
Multi-mode Multi-corner (MMMC), Clock Tree Synthesis (CTS), Static Timing Analysis (STA), Shell, Python, Routing, Perl, Tcl, OCV, primetime, Power Grid Analysis, Fusion Compiler, ICC2, Tempus, Voltus, Innovus, SDC, Static Dynamic IR Drop, Placement, Setup Hold, POCV, RedHawk-SC, floorplanning, Physical Design, Timing Closure, EDA Tools, AOCV
Skills:
Tcl Scripting, Perl, Python, primetime, ICC2, Cadence Innovus, Tempus, Synopsys Fusion Compiler, Synthesis, Ansys RedHawk, Timing Analysis, Physical Design Implementation
Skills:
Unix, Ilm, Linux, Tcl, Python Scripting, QRC models, back-annotation, Multi-Vt, SPEF correlation, Cadence Tempus, Tempus SI, voltage island timing, ETM, OCV, Timing ECO methodology, Advanced nodes 12nm or below, STA fundamentals, glitch, CTS timing implications, MMMC, SDC expertise, crosstalk, Cadence Conformal ECO, Physical-aware Tempus experience, POCV, Innovus–Tempus in-design timing, AOCV