ASIC Engineer, Devices and Services

Role Responsibilities

• Plan and execute the verification of next-generation Infrastructure IPs, interconnects, and memory subsystems.
• Develop constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM).
• Design and enhance cross-language tools and scalable verification methodologies.
• Collaborate with design engineers to debug tests and ensure verification progress toward tape-out.

Job Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• Experience in verifying digital systems, RTL verification using SystemVerilog or C/C++, and using scripting languages.
• Familiarity with performance verification of SOCs, pre-Silicon analysis, and post-Silicon correlation.
• Proficient in creating verification components and environments using standard verification methodologies like UVM and SystemVerilog.