ASIC Engineer, Design Verification
ASIC Engineer, Design Verification
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Job Description
Meta is looking for ASIC Engineer, Formal Verification to join our dynamic team and embark on a rewarding career journey.
- Develop and implement ASIC design methodologies, including design, verification, and testing
- Collaborate with cross-functional teams to identify and understand requirements and develop solutions that meet business needs
- Develop and maintain design specifications, test plans, and documentation
- Participate in the full ASIC development cycle, including architecture, RTL design, verification, and synthesis
- Perform design optimization and analysis to ensure optimal performance and power efficiency
- Ensure compliance with industry standards and guidelines.
- Strong knowledge of ASIC design methodologies and tools.
- Excellent communication and interpersonal skills Strong analytical and problem-solving skills
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Key Skills
ASIC development cycle
ASIC design methodologies
About Company
Skills:
code coverage , Oops, Usb, Networking, Cpu, DDR, Pcie, Verilog, Ethernet, Arm, LINT, cdc, SV, SV METH, C tests, Axi, AMBA, spyglass, VHDL, SoC Verification, Graphics, RTL Coding, AHB
Skills:
C, C++, Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, Post-silicon debugging, RTL design and verification flows, Simulation Tools, JTAG protocols, Digital Design, Assembly language programming
Skills:
Tcl Scripting, System Verilog, Synopsys Mentor VIPs, verification methodologies, performance power optimization, random constraint-based testing, PCIe Gen3 Gen4 Gen5 Gen6, SMMU, Coresight architecture, Uvm, assertion-based verification, CHI protocols, UPF, Axi, formal verification, CXL 1.1 2.0 3.0, power-aware verification, coverage-driven testing, SVA
Skills:
Jtag, C, Verilog, System Verilog, Uvm, SOC RTL Design Verification
Skills:
Computer Architecture, C, Assembly Language, Vcs, Perl, Verilog, Python, System Verilog, Computer Engineering, Raven, UVM methodology, ACK, Microelectronics, Questa, Electrical Engineering